1. Technical Field
The present invention relates to memory controllers in general. More particularly, the present invention relates to extreme data rate (XDR) memory controllers. Still more particularly, the present invention relates to an XDR memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to XDR memory devices.
2. Description of Related Art
A memory controller is typically utilized to regulate access requests (i.e., reads and writes) on memory devices from various requesting devices. After receiving an access request along with address and control information from a requesting device, the memory controller decodes the address information into bank, row and column addresses. The memory controller then sends address and control signals to the appropriate memory devices for performing the requested memory operation. For a read operation, the memory controller sends the read command and then returns the read data retrieved from the memory devices to the requesting device. For a write operation, the memory controller sends the write data to the memory devices along with the write command.
When performing a read or write operation, the memory controller is responsible for generating an appropriate sequence of control signals for accessing the desired addresses within the memory devices. The sequence of control signals for an operation typically involves activating (or opening) a row of a bank within the memory devices, then writing to or reading from the selected columns in the activated row, and finally precharging (or closing) the activated row.
Over the years, several types of dynamic random access memories (DRAMs) have been developed, such as double data rate (DDR) DRAMs, extreme data rate (XDR) DRAMs, etc. Details on XDR DRAM devices can be found in XDR DRAM specifications promulgated by Rambus7. It is up to designers of XDR memory controllers to not only meet the XDR DRAM specifications, but to also satisfy other design requirements such as area, power, timing, performance, etc. An “open command cycle” means that a packet may be issued on a request bus to XDR DRAMs because no other packet is currently occupying the bus. In general, there is one command per packet, although a notable exception is that two precharge commands may be contained in one precharge packet. The present disclosure provides an XDR memory controller capable of locating an open command cycle to issue a precharge packet.